`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/15 10:27:47
// Design Name: 
// Module Name: Latch32
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Latch32(
    input   wire        clk,
    input   wire        rst,
    input   wire        pause,

    input   wire [31:0] in,
    output  wire [31:0] out
    );
    
    reg [31:0] temp;
    
    assign out = temp;
    
    always @(posedge clk) begin
        if (rst == 0) begin
            temp <= 0;
        end else begin
            if (pause == 0) begin
                temp <= in;
            end
        end
    end
    
endmodule
